搜索资源列表
testbenchcpu8080
- this is code testbench cpu -this is code testbench cpu 8080
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
COMPRESSION
- Simple LZW image compression implemented on Spartan-3e starter kit using Xilinx9.2 and Modelsim for testbench simulation.
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
mini_aes_latest[1].tar
- AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
GUI_Matting
- matlab编写的交互式image matting程序，包括：Poisson，Hillman，Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
DDC
- 直接数字频率合成dds源码，cos三角函数生成代码，及测试代码，用于ddc前端测试的testbench。-direct digital frequency sysnthesis
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
alu
- ALU modeling verilog codes and testbench
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
scrambleanddescrambler
- 适合802.11a的scrambler与descrambler的设计，适合OFDM系统设计的初学者，有testbench可供参考-The scrambler and descrambler for 802.11a design, OFDM system design for beginners, there are available for reference testbench
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
i2c-IPcore
- i2c的完整可用的Verilog代码，包含testbench.-i2c complete Verilog code is available, including the testbench.
USB
- 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.